SignalPU: A programming model for DSP applications on parallel and heterogeneous clusters

International audience—The biomedical imagery, the numeric communi-cations, the acoustic signal processing and many others digital signal processing applications (DSP) are present more and more everyday in the numeric world. They process growing data volume which is represented with more and more accuracy, and using complex algorithms with time constraints to satisfying. Con-sequently, a high requirement of computing power characterize them. To satisfy this need, it's inevitable today to use parallel and heterogeneous architectures in order to speed-up the processing, where the best examples are the supercomputers like "Tianhe-2" and "Titan" of the ranking top500. These architectures with their multi-core nodes supported by many-core accelerators offer a good response to this problem, but they are still hard to program in order to make performance because of lot of things like synchronization, the memory management, the hardware specifications . . . In the present work, we propose a high level programming model to implement easily and efficiently digital signal processing applications on heterogeneous clusters

A Computation Core for Communication Refinement of Digital Signal Processing Algorithms

International audienceThe most popular Moore's law formulation, which states the number of transistors on integrated circuits doubles every 18 months, is said to hold for at least another two decades. According to this prediction, if we want to take advantage of technological evolutions, designer's productivity has to increase in the same proportions. To take up this challenge, system level design solutions have been set up, but many efforts have still to be done on system modelling and synthesis. In this paper we propose a computation core synthesis methodology that can be integrated on the communication refinement steps of electronic system level design tools. In the proposed approach, computation cores used for digital signal processing application specifications relying on coarse grain communications and synchronizations (e.g. matrix) can be refined into computation cores which can handle fine grain communications and synchronizations (e.g. scalar). Its originality is its ability to synthesize computation cores which can handle fine grain data consumptions and productions which respect the intrinsic partial orders of the algorithms while preserving their original functionalities. Such cores can be used to model fine grain input output overlapping or iteration pipelining. Our flow is based on the analysis of a fine grain signal flow graph used to extract fine grain synchronizations and algorithmic expressions

Design exploration and HW/SW rapid prototyping for real-time system design

Embedded signal processing systems are usually associated with real-time constraints and/or high data rates such that fully software implementation are often not satisfactory. In that case, mixed hardware/software implementations are to be investigated. However the increasing complexity of current applications makes classical design processes time consuming and consequently incompatible with an efficient design space exploration. To address this problem, we propose a system-level design based methodology that aims at unifying the design flow from the functional description to the physical HW/SW implementation through functional and architectural flexibility. Our approach consists in automatically refining high abstraction level models through the use of an electronic system-level (ESL) design tool according to function models from the one hand and prototyping platform models from the other hand. We illustrate our methodology with the design of a wireless communication system. We provide design results showing the variety of dedicated architectures that can be investigated with this design flow

Task migration of DSP application specified with a DFG and implemented with the BSP computing model on a CPU-GPU cluster

International audienceNowadays computer applications are becoming heavier and require, at the same time, real-time results. The Heterogeneous clusters with their computing power represent a good solution to this request. However, it is possible that during the execution, a computing element of the cluster becomes defaulting, needs maintenance, or that the load needs to be re-balanced. . . In this paper, we propose a migration strategy for relocating the execution of a task to another computing element. In particular, we are interested in remap nodes of Data Flow Graph (DFG), representing Digital Signal Processing (DSP) application, onto heterogeneous (CPU-GPU) clusters while keeping up the flow of data and minimizing the temporal perturbation. For our approach, we give a lower bound for the flow of data after the migration and, validate it by the real-time construction of visual saliency map from video input

Hardware communication refinement in digital signal processing, modelling issues

In this paper we present the different modelling problems which a Digital Signal Processing (DSP) application designer has to tackle while refining an abstract specification relying on coarse grain data (e.g. matrices) toward a hardware implementation model relying on fine grain data (e.g. scalar). To address this problematic, we propose a modelling framework which can be used to refine an algorithm specified with coarse grain interfaces to a form which allow, from the functionnality point of view, to model all its fine grain hardware implmentation

Séquenceur mémoire pour applications multimédias temps réel gérant les séquences d'accès indéterministes

Dans le domaine du traitement du signal et de l'image, les applications multimédias sont souvent caractérisées par un grand nombre d'accès aux données. Pour la plupart de ces applications, les accès aux données structurées (tableaux, vecteurs) sont réguliers et périodiques. Dans ces conditions, il est possible et efficace de générer des contrôleurs pipeline d'accès à la mémoire. Cette technique est utilisée afin d'améliorer les accès en mode pipeline autorisés par les mémoires actuelles. On utilise pour cela des composants matériels dédiés pour générer les adresses et pour packer/dépacker les données. Dans cet article nous présentons l'architecture d'un séquenceur mémoire qui permet de prendre en compte de manière efficace les accès prédictibles aussi bien que les séquences d'accès non prédictibles (calculs d'adresses dynamiques) de manière pipeline

Symmetric microwave potentials for interferometry with thermal atoms on a chip

International audienceA trapped atom interferometer involving state-selective adiabatic potentials with two microwave frequencies on a chip is proposed. We show that this configuration provides a way to achieve a high degree of symmetry between the two arms of the interferometer, which is necessary for coherent splitting and recombination of thermal (i.e., noncondensed) atoms. The resulting interferometer holds promise to achieve high contrast and long coherence time, while avoiding the mean-field interaction issues of interferometers based on trapped Bose-Einstein condensates

Etude de l'Influence du Stress sur la Créativité dans un Scénario en Réalité Virtuelle

Whether it is for evolution, competitiveness or problem solving, innovation is necessary to a company’s survival. Thus, it is essential to understand this process and what affect them to improve innovation. In this paper we focus on the ideation steps (generating ideas and proposing new concepts). We developed an experimental protocol in Virtual Reality, as it has been demonstrated to be a useful medium for creativity. We conducted the experiment following two conditions, one with an induction of stress and one without, to evaluate the effect of stress on the level of creativity. The levels of stress, creativity and physiological signals have been monitored. Our early results did not show significant differences between the two groups, however, as supported by previous studies, we have successfully used the Empatica E4 physiological wearable in our experimental context and observed a general rise in electro-dermal activity (EDA) among our participants. We suggest that our experiment was able to elicit an emotional response in our participants that is observable in the physiological data. This preliminary study will help us shape the next steps of our research on the understanding of the creativity experience depending on different parameters

Studying the Influence of Stress on Creativity in a Virtual Reality Scenario

Whether it is for evolution, competitiveness or problem solving, innovation is necessary to a company’s survival. Thus, it is essential to understand these processes and what affects them in order to improve innovation. In this paper we focus on the ideation steps (generating ideas and proposing new concepts). We developed an experimental protocol in Virtual Reality, as it has been demonstrated to be a useful medium for creativity. We conducted the experiment following two conditions, one with an induction of stress and one without, to evaluate the effect of stress on the level of creativity. The levels of stress, creativity and physiological signals have been monitored. Our early results did not show significant differences between the two groups, however, as supported by previous studies, we have successfully used the Empatica E4 physiological wearable in our experimental context and observed a general rise in electrodermal activity (EDA) among our participants. We suggest that our experiment was able to elicit an emotional response in our participants that is observable in the physiological data. This preliminary study will help us shape the next steps of our research on the understanding of the creativity experience depending on different parameters